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[Other] DDS

Description: 附件包括1.基于FPGA实现DDS正弦波产生2.对应程设计说明一份3.重要说明一份。使用的软件平台为ISE13.3，硬件平台为Xilinx公司的V4板子。-DDS generator
Platform: | Size: 5718016 | Author: zhulinglei | Hits:

[VHDL-FPGA-Verilog] r7lite

Description: R7Lite是基于Xilinx的Kintex7系列FPGA的PCI Express参考设计代码，PCIe 2.0 4x模式，包括了FPGA实现，Linux下驱动和测试例程。-R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing App
Platform: | Size: 21678080 | Author: yao | Hits:

[Other] FPGA_learning_books

Description: learn and master Field programmable gate arrays (FPGAs). hand-book for starters 2 of the biggest FPGA companies i.e Altera & Xilinx- learn and master Field programmable gate arrays (FPGAs). hand-book for starters 2 of the biggest FPGA companies i.e Altera & Xilinx
Platform: | Size: 19569664 | Author: umair | Hits:

[Other] PCIExpressBaser21

Description: PCIe standard version 2.1. Xilinx axi bridge for pcie.
Platform: | Size: 3430400 | Author: feka | Hits:

[VHDL-FPGA-Verilog] VHDL-projects

Description: I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
Platform: | Size: 1505280 | Author: Jaroslav | Hits:

[VHDL-FPGA-Verilog] 16FFT

Description: Xilinx的16点傅里叶分析，内有详细说明-The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum.
Platform: | Size: 739328 | Author: 我是谁 | Hits:

[VHDL-FPGA-Verilog] 1024FFT

Description: Xilinx的1024点傅里叶分析，内有详细说明-The xFFT1024 fast Fourier transform (FFT) Core computes a 1024-point complex FFT. The input data is a vector of 1024 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum
Platform: | Size: 700416 | Author: 我是谁 | Hits:

[VHDL-FPGA-Verilog] 8-TFT_24

Description: 基于Xilinx Spartan6自制开发板实验，2.4存TFT屏静态刷新特定图片。如果要修改图片，请使用Matlab将图片生成*.coe格式，生成ROM加载。-Development board based on Xilinx Spartan6 homemade experiment, 2.4 TFT screen kept static refresh specific picture. If you want to modify the picture, the image is generated using Matlab* .coe format, generate ROM loaded.
Platform: | Size: 1344512 | Author: 康二栋1号 | Hits:

[Editor] New-WinRAR-archive-(3)

Description: xilinx code for Design a 4:1 multiplex using 2:1mux.This code tested on cadence tool also.
Platform: | Size: 24576 | Author: mahesh | Hits:

[VHDL-FPGA-Verilog] project-main-doc

Description: The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is possible to reduce the input data. To compress the original input data or to reduce the input data it will never effect the original information and it is possible to consume less power for data transmission. It is possible to transmit the data efficiently by using these methods here two compression methods are there. 1) Lossless compression and 2) Lossy compression method. In this project to compress the input data by using lossless compression technique. To this project by using Xilinx 9.1i simulator and to write the code by using VHDL module-The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is possible to reduce the input data. To compress the original input data or to reduce the input data it will never effect the original information and it is possible to consume less power for data transmission. It is possible to transmit the data efficiently by using these methods here two compression methods are there. 1) Lossless compression and 2) Lossy compression method. In this project to compress the input data by using lossless compression technique. To this project by using Xilinx 9.1i simulator and to write the code by using VHDL module
Platform: | Size: 207872 | Author: gowtham | Hits:

[VHDL-FPGA-Verilog] Runlength-Data-Compression

Description: The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is possible to reduce the input data. To compress the original input data or to reduce the input data it will never effect the original information and it is possible to consume less power for data transmission. It is possible to transmit the data efficiently by using these methods here two compression methods are there. 1) Lossless compression and 2) Lossy compression method. In this project to compress the input data by using lossless compression technique. To this project by using Xilinx 9.1i simulator and to write the code by using VHDL module.-The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is possible to reduce the input data. To compress the original input data or to reduce the input data it will never effect the original information and it is possible to consume less power for data transmission. It is possible to transmit the data efficiently by using these methods here two compression methods are there. 1) Lossless compression and 2) Lossy compression method. In this project to compress the input data by using lossless compression technique. To this project by using Xilinx 9.1i simulator and to write the code by using VHDL module.
Platform: | Size: 207872 | Author: gowtham | Hits:

[VHDL-FPGA-Verilog] snake

Description: 自己写的verilog贪吃蛇程序，使用vivado2015.2软件编写综合的，硬件平台是xilinx的basys3平台，当检测到碰撞时，led灯会亮起-Write your own verilog Snake program, using the software to prepare a comprehensive vivado2015.2, the hardware platform is the basys3 xilinx platform, when a collision is detected, led lights up
Platform: | Size: 3788800 | Author: 范赛龙 | Hits:

[source in ebook] XilinxPFPGAKaiFaShiYongJiaoCheng

Description: 《Xilinx FPGA开发实用教程（第2版）》所附源码-XILINX FPGA
Platform: | Size: 24898560 | Author: dfdqzp | Hits:

[Open-source hardware] dwt

Description: Running: C:\Xilinx_Installed\14.3\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe -prj G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_beh.prj work.top_dwt work.glbl ISim P.40xd (signature 0x8ef4fb42) Number of CPUs detected in this system: 2 Turning on mult-threading, number of parallel sub-compilation jobs: 4 Determining compilation order of HDL files
Platform: | Size: 3072 | Author: farrokh | Hits:

[Embeded-SCM Develop] dwt2d

Description: secureip -o G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe -prj G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_beh.prj work.top_dwt work.glbl ISim P.40xd (signature 0x8ef4fb42) Number of CPUs detected in this system: 2 Turning on mult-threading, number of parallel sub-compilation jobs: 4 Determining compilation order of HDL files
Platform: | Size: 2048 | Author: farrokh | Hits:

[VHDL-FPGA-Verilog] help_lib

Description: 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)
Platform: | Size: 7014400 | Author: Nanke42 | Hits:

[ARM-PowerPC-ColdFire-MIPS] PipelineCPU

Description: 1. understand how to improve CPU performance 2. master the working principle of pipelined MIPS microprocessor. 3. understand the concept of data adventure, control risk and the solution of pipeline conflict. 4. mastering the testing method of pipelined MIPS microprocessor(this file contains 3 packs,which is developed in Xilinx ISE contain the basic functions of a typical CPU 5 stages:IF,ID,EX,MEM,WB for education only)
Platform: | Size: 633856 | Author: D.FRANCIS | Hits:

[VHDL-FPGA-Verilog] xapp_hls_Matrix Multiply

Description: This repository includes a pure Vitis HLS implementation of matrix-matrix multiplication (A*B=C) for Xilinx FPGAs, using Xilinx Vitis to instantiate memory and PCIe controllers and interface with the host. Experiments run on a VCU1525 achieved 462 GFLOP/s, 301 GFLOP/s and 132 GFLOP/s for half, single, and double precision, respectively, with routing across the three SLRs being the primary bottleneck preventing further scaling. The code is not device-specific, and can be configured for any Xilinx FPGA supported by the Xilinx OpenCL runtime. Kernels have also been verified to execute on TUL KU115, Alveo U250, and Alveo U280 boards with similar results. The implementation uses a systolic array approach, where linearly connected processing elements compute distinct contributions to the outer product of tiles of the output matrix. The approach used to implement this kernel was presented at FPGA'20 [1]. For a general description of the optimization techniques that we apply, we refer to our article on HLS transformations [2]. We also gave a tutorial on HLS for HPC at SC'21, ISC'21, SC'20, HiPEAC'20, SC'19, SC'18, and PPoPP'18.
Platform: | Size: 585044 | Author: 1679556379@qq.com | Hits:
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